Dec. 3, 2024 – Beaverton, Ore. – The CXL Consortium, an industry standard body focused on coherent connectivity, announces the release of its Compute Express Link (CXL) 3.2 Specification. The 3.2 Specification optimizes CXL Memory Device monitoring and management, enhances functionality of CXL Memory Devices for OS and Applications, and extends security with the Trusted […]

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Along with his article to be found on this site, technology analyst Adrian Cockcroft of OrionX (and former AWS vice president) joins Shahin and Doug after SC23 to discuss TOP500 trends, the AI-HPC crossover, liquid cooling, chiplets, and the emergence of UCIe and CXL – some of the anticipated advancements are truly eye-popping. In this podcast, sponsored by Lenovo, the relentless pursuit of higher performance, the acceleration in the pace of change in high performance processing, is examined.

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We’ve heard so much about the CXL interconnect – including the recent announcement of CXL v3.0 – and components that are CXL-ready, that it may come as a surprise that CXL v1.1 “hosts” are only just now shipping. It’s a technology that could play a central role in the ever-more heterogenous, more memory-intensive systems of the future. And now, after several years of experimentation and various interconnect consortia, CXL is emerging as the standard for advanced functionality for fabric technologies. Along with CXL we also discuss some of the details of the CHIPS and Science Act....

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Researchers at Pacific Northwest National Laboratory (PNNL) and Micron are are developing an advanced memory system to support AI for scientific computing. The work is designed to address AI’s insatiable demand for live data — to push the boundaries of memory-bound AI applications — by connecting memory across processors in a technology strategy utilizing the […]

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The post Astera Labs Claims 1st CXL 2.0 Memory Accelerator SoC Platform appeared first on High-Performance Computing News Analysis | insideHPC.